Semiconductor device comprising power elements in juxtaposition order

ABSTRACT

A semiconductor device including a multiplicity of large current power elements with each power element divided into a multiplicity of divisional elements and arranged such that the power elements belonging to different power elements are arranged in a repetitive sequential order. The IC chip of the semiconductor device is formed to have output wires extending from the respective divisional elements connected to corresponding output pads without crossing other output wires. Arranged on the IC chip are output bumps in association with the respective output pads. A rewiring layer is provided having output coupling wires for connecting together the bumps that belong to the same power element and connecting them further to an external output electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 14/821,493,filed on Aug. 7, 2015, which is a divisional of application Ser. No.11/778,526, filed on Jul. 16, 2007, now abandoned, which is acontinuation of application Ser. No. 10/962,162, filed on Oct. 8,2004,now U.S. Pat. No. 7,265,395, and claims the benefit of priorityunder 35 USC 119 of Japanese application no. 2003-358599, filed on Oct.20, 2003. The entire contents of all these applications are incorporatedherein by reference in their entirety.

FIELD OF THE INVENTION

This invention relates to a semiconductor device equipped with amultiplicity of large current power elements (i.e. large capacity powerelements) such as power transistors.

BACKGROUND OF THE INVENTION

Some semiconductor devices have a multiplicity of large current powerelements such as power transistors arranged in close proximity (see forexample Japanese Patent Early Publication No. H7-135299).

These multiple large current power elements are often required to havetheir relative variations in characteristics reduced. One way to reducethe relative variations is shown in FIG. 8.

FIG. 8 shows an arrangement of a semiconductor integrated circuit 200having two power transistors 1A and 1B. Operating conditions of thepower transistors 1A and 1B are controlled by respective control signalssupplied, via signal lines 3A and 3B, from respective control circuits2A and 2B each having a signal-processing circuit and a pre-drivecircuit. The output end of the power transistor 1A is connected to anoutput pad 5A via an output wire 4A, and the output end of the powertransistor 1B to output pad 5B via an output wire 4B. The power inputends of the power transistors 1A and 1B are connected to a common powersupply pad 7 via power supply wires 6. The power input end may bealternatively connected to the ground. In this case, the power inputends serve as grounding ends, the power supply wires 6 as groundingwires, and the power supply pad 7 as a grounding pad. This applies tothe rest of the examples shown below.

In the conventional semiconductor device 200, the power transistors 1Aand 1B are arranged as close as possible to each other. However, nomatter how closely the power transistors 1A and 1B are arranged to eachother, corresponding portions of the power transistors 1A and 1B(indicated by Xa and Xb in FIG. 8 for example) will be separated by anappreciable distance, since the power transistors 1A and 1B themselveshave large areas. In addition, the semiconductor substrate in which thepower transistors 1A and 1B are built has impurity gradient inducedduring its manufacture. Variations in characteristics of the powertransistors 1A and 1B due to the impurity gradient and distance areunavoidable. Similarly, variations in the characteristics due to atemperature gradient created in the semiconductor substrate duringoperation are unavoidable.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a semiconductordevice including a multiplicity of large current power elements such aspower transistors whose relative variations in characteristics aresmall.

It is another object of the invention to provide a semiconductor deviceincluding a multiplicity of large current power elements whose relativevariations in characteristics are small and having output wiresconnecting the power elements without crossing one another to reducetheir layout area.

A semiconductor device in accordance with one embodiment of theinvention includes a multiplicity N (N≧2) of semiconductor powerelements adapted to perform N different operations, wherein each of theN power elements is divided into M (M≧2) divisional elements and N×Mdivisional elements are arranged such that divisional elements belongingto different power elements are sequentially arranged in juxtaposition.The semiconductor device further comprises N output pads in associationwith the N power elements, and output wires for connecting thedivisional elements that belong to a respective semiconductor powerelement to an output pad associated with power element.

The semiconductor device may be provided with power supply wires orgrounding wires for connecting the N×M divisional elements to at leastone power supply pad or one grounding pad, respectively, wherein thepower supply wires and grounding wires are formed using a wiring layerdifferent from the wiring layer for the output wires.

A semiconductor device in accordance with another embodiment of theinvention comprises:

a semiconductor integrated circuit (IC) body including

-   -   a multiplicity N (N≧2) of semiconductor power elements adapted        to perform N different operations with each power element        divided into M (M≧2) divisional elements and with N×M divisional        elements arranged such that divisional elements belonging to        different power elements are sequentially arranged in        juxtaposition, and    -   output wires for connecting the N×M divisional elements to        associated N×M output pads without crossing one another; and

a rewiring layer provided on the IC body and having

-   -   output bumps electrically connected to the respective N×M output        pads to retrieve the outputs of the N×M divisional elements, and    -   output coupling wires, provided on an insulating layer formed on        the IC body, for connecting together the output bumps that        belong to the same power element, the output coupling wires        further connecting to an external output electrode for        connection with an external device.

The IC body may have power supply wires or grounding wires forconnecting the N×M divisional elements to at least one power supply pador one grounding pad, the power supply wires and grounding wires formedusing a wiring layer different from the wiring layer for the outputwires.

The IC body may have power supply wires or grounding wires forconnecting the N×M divisional elements to at least one power supply pador a grounding pad. The rewiring layer may be provided with a powersupply bump or a grounding bump for electrical connection with the powersupply pad or the grounding pad. The power supply pad or the groundingpad is connected to an external power supply electrode or externalgrounding electrode.

The power supply wires or grounding wires are arranged not to cross anyof the output wires on the same plane.

Each of the N×M output pads may be arranged at an angular positionrelative to the divisional element associated with the output pad, theangular position being unique to the divisional elements that belong tothe same power element and different from the angular positions ofdivisional elements belonging to other power elements.

Each of the N×M power supply pads or grounding pads may be arranged atan angular position relative to the divisional element associated withthe power supply pad or grounding pad, the angular position being uniqueto the divisional elements that belong to the same group and differentfrom the angular positions of the output pads.

The output coupling wires may be formed of the same material as theoutput bumps after the output bumps and the insulating layer are formed.

The external output electrode may be a ball electrode.

As described above, the inventive semiconductor device has amultiplicity of large current power element such as power transistors,with each power element divided into a multiplicity of divisionalelements, wherein the divisional elements belonging to different powerelements are sequentially arranged in juxtaposition to reduce relativevariations of the characteristics of the power elements.

According to the invention, in a semiconductor device having amultiplicity of large current power elements such as power transistorswith each power element divided into multiple groups of divisionalelements and with divisional elements belonging to different powerelements are sequentially arranged in juxtaposition, and in suchsemiconductor device, output wires of the divisional elements arearranged not to cross one another. This arrangement enables reduction ofthe layout area of the power elements, along with the reduction of therelative variations of the characteristics of the power elements.

The IC body of inventive semiconductor device including a multiplicityof semiconductor power elements is provided thereon with a rewiringlayer having output coupling wires for connecting together divisionalelements belonging to the same power element. Accordingly, thesemiconductor device of the invention can be used in the same way as anordinary semiconductor IC.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a structure of the IC chip according to a first embodimentof the invention.

FIG. 2A shows a structure of the IC chip body according to a secondembodiment of the invention.

FIG. 2B shows a structure of the rewiring layer formed on the IC chipbody of the second embodiment.

FIG. 3 shows a schematic sectional view illustrating a structure of thesemiconductor device according to the second embodiment.

FIG. 4 shows a structure of the IC chip body according to a thirdembodiment of the invention.

FIG. 5A shows a structure of the IC chip body according to a fourthembodiment of the invention.

FIG. 5B shows a structure of the rewiring layer formed on the IC chipbody of the fourth embodiment.

FIG. 6A shows a structure of the IC chip body according to a fifthembodiment of the invention.

FIG. 6B shows a structure of the rewiring layer formed on IC chip bodyof the fifth embodiment.

FIG. 7A shows a structure of the IC body according to a sixth embodimentof the invention.

FIG. 7B show a structure of the rewiring layer formed on the IC chipbody of the sixth embodiment.

FIG. 8 shows a structure of a conventional IC chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The inventive semiconductor device will now be described in detail byway of example with reference to the accompanying drawings.

FIG. 1 shows a structure of the semiconductor device according to afirst embodiment of the invention, which includes a multiplicity ofpower elements adapted to perform different operations and provide theirown outputs. To reduce relative variations in characteristics of thepower elements, each power element is divided into a multiplicity ofdivisional elements and arranged in such a way that divisional elementsthat belong to different power elements are arranged in juxtapositionand in a repetitive sequential order. Of course, the power elements canbe configured to operate simultaneously. These features are common inany of the embodiments of the invention described below.

FIG. 1 shows a structure of a semiconductor integrated circuit(hereinafter referred to as IC chip) 100 having two power transistors 1Aand 1B consisting of divisional elements 1A-1 and 1A-2 and divisionalelements 1B-1 and 1B-2, respectively. The divisional elements belongingto the power transistors 1A and 1B are arranged in juxtaposition in theorder of 1A-1, 1B-1, 1A-2, and 1B-2, as shown.

The two divisional elements 1A-1 and 1A-2 are connected together by asignal wire 3A and an output wire 4A to form the power transistor 1A.The two divisional elements 1B-1 and 1B-2 are connected together by asignal wire 3B and an output wire 4B to form the power transistor 1B.Power supply wires 6, shown by phantom lines, are formed using a wiringlayer different from the wiring layer for the output wires 4A and 4B,and connected to all the divisional elements 1A-1-1B-2. The output wires4A and 4B are respectively connected to output pads 5A and 5B, and thepower supply wires 6 are connected to a power supply pad 7. Otherfeatures of the IC chip of FIG. 1 are the same as those of FIG. 8. Itshould be understood that the power supply wires shown by dashed linesin any other embodiment are also formed using a different wiring layerthan the wiring layer for the output wires.

In the IC chip 100, the divisional element 1A-1 or 1A-2 belonging to thepower transistor 1A and the divisional element 1B-1 or 1B-2 belonging tothe power transistor 1B are arranged in juxtaposition. As a result, thedistance between two corresponding portions (e.g. between portions Xa-1and Xb-1, and between Xa-2 and Xb-2 of FIG. 1) becomes approximately onehalf the conventional distance between them. Now variations incharacteristics of the two transistors exist between two correspondenceportions of the elements, for example between Xa-1 and Xb-1 and betweenXa-2 and Xb-2. Thus, the variations in the characteristics of the powertransistors 1A and 1B are reduced accordingly.

In the first embodiment, however, although the variations in thecharacteristics are improved, improvement is not satisfactory regardingthe following points. In the first embodiment, the output wires 4A and4B extending from the divisional elements 1A-1-1B-2 are preferablyconnected to the output pads 5A and 5B with as small variation inresistance as possible. In doing so, if the output pads arranged in thesame angular position relative to the respective divisional elements,the output wires 4A and 4B connected to the output pads will cross eachother if the same wiring layer is used. Moreover, if the power supplywires 6 are provided using the same wiring layer, they will cross theoutput wires 4A and 4B. Furthermore, the output wires 4A and 4B and thepower supply wires 6 are required to have sufficient widths in order tosuppress on-resistances of the power elements. However, since the wiringdistances of the wires increase when such crossing of wires takes place,the widths of the lead wires must be increased to keep theon-resistances suppressed. Hence, when the output wires 4A and 4B andthe power supply wires 6 are arranged in the regions between thedivisional elements 1A-1-1B-2 and the output pads 5A and 5B, or betweenthe divisional elements 1A-1-1B-2 and the power supply pad 7 as shown inFIG. 1, a large wiring area is needed in the region, thereby loweringthe layout efficiency.

FIGS. 2A and 2B together show a structure of the semiconductor deviceaccording to a second embodiment of the invention configured to reducethe relative variations in characteristics of the power elements whilesuppressing the layout area therefore. FIG. 3 is a schematic sectionalview of a semiconductor device of the second embodiment.

FIG. 2A particularly shows the structure of a semiconductor integratedcircuit (referred to as IC chip body) according to the invention. FIG.2B particularly shows the structure of a rewiring layer formed on the ICchip body. In the following embodiments, power elements are supposed tobe power transistors. However, the invention may be applied to otherpower elements other than power transistors in reducing their relativevariations in characteristics.

In the example shown in FIG. 2A, each of the N (N=2) power transistors11A and 11B consists of two divisional elements (M=2). The multipledivisional elements 11A-1, 11B-1, 11A-2, and 11B-2 of the powertransistors 11A and 11B are arranged in juxtaposition in the ordermentioned. The two divisional elements 11A-1 and 11A-2 are controlled bythe control signal supplied from a control circuit 12A via a signal wire13A. That is, the divisional elements 11A-1 and 11A-2 are driventogether as a unified power transistor 11A. The two divisional elements11B-1 and 11B-2 are controlled by a control signal supplied from acontrol circuit 12B via a signal wire 13B. That is, the divisionalelements 11B-1 and 11B-2 are driven together as a unified powertransistor 11B.

The output wires 14A-1, 14B-1, 14A-2, and 14B-2 of the divisionalelements 11A-1 1-B-2 are respectively connected to output pad 15A-1,15B-1, 15A-2, and 15B-2.

Moreover, power supply wires 16 extending from the divisional elements11A-1-11B-2 are connected to a common power supply pad 17 using a wiringlayer different from the wiring layer for the output wires 14A-1-14B-2.Incidentally, the “power supply” can alternatively be replaced by the“ground.” In this case, the power supply pad 17 is grounded, and thepower supply wire 16 is rephrased as the grounding wire 16 and the powersupply pad 17 as the grounding pad 17. This applies to other embodimentsof the invention.

In the IC chip body 10, the divisional elements 11A-1 and 11A-2belonging to the power transistor 11A and the divisional elements 11B-1and 11B-2 belonging to the power transistor 11B are arranged in closeproximity. The corresponding portions (as marked as Xa-1 and Xb-1, andXa-2 and Xb-2 in FIG. 2A) have short distances. That is, variations incharacteristics of the two transistors exist between two correspondenceportions of the elements, for example between Xa-1 and Xb-1 and betweenXa-2 and Xb-2.

In the IC chip 10, output wires 14A-1-14B-2 extending from thedivisional elements 11A-1-11B-2 are directly connected to the outputpads 15A-1-15B-2. That is, the output wires 14A-1-14B-2 do not crosseach other. Thus, on-resistances of the power transistors 11A and 11Bincluding resistances of the wiring resistances can be minimized.

It is noted that the output wires 14A-1-14B-2 cross the power supplywires 6. However, in the IC chip body 10, crossing does not matter,since the electric conduction layer for the output wires and that forthe power supply wire are formed using different wiring layers.

In a rewiring layer 20 formed on the IC chip body shown in FIG. 2B,output bumps (or output posts) 21A-1, 21B-1, 21A-2, 21B-2, and a powersupply bump (or power supply post) 23 are provided in contact withcorresponding output pads 15A-1, 15B-1, 15A-2, and 15B-2 and with acorresponding power supply pad 17, respectively. An insulating layer ofpolyimide resin for example is provided on the surface of the IC chipbody 10 excluding the areas of the pads. This insulating layer may havea thickness comparable with the heights of the output bumps 21A-1-21B-2and the power supply bump 23.

The output bumps 21A-1-21A-2 associated with the power transistor 11Aare connected together by an output coupling wire 22A, which is extendedto a position where it is connected to an external output electrode 24A.The bumps 21B-1 and 21B-2 associated with the power transistor 11B areconnected together by an output coupling wire 22B, which is extended toa position where it is connected to an external output electrode 24B.The power supply bump 23 is connected to a power supply bump electrode25. It is noted that in this rewiring layer 20 the output coupling wires22A and 22B do not cross each other or cross any other lead wires.Therefore, the output coupling wires can be formed with sufficientwidths in one layer to minimize their resistances.

It is noted that the external output electrodes 24A and 24B canalternatively be provided directly on the respective bumps 21A-1 and21A-2 or on the respective bumps 21B-1 and 21B-2.

The output coupling wires 22A and 22B are formed after the output bumps21A-21B and the insulating layer are formed. The output coupling wires22A and 22B are preferably formed of the same material, and formed tohave the same thickness and the same length as the bumps. The externaloutput electrodes 24A and 24B and the power supply bump electrode 25 maybe provided in the form of, for example, ball electrodes and a bumpelectrode, respectively.

FIG. 3 is a schematic sectional view illustrating the structure of thesemiconductor device shown in FIGS. 2A and 2B, with alphabets A and Bomitted from the symbols.

As shown in FIG. 3, each of the constituent elements of FIG. 2A is builtin the IC chip body 10. Formed on the surface of the IC chip body 10 arethe output pads 15. The bumps (or posts) 21 are formed to be inelectrical contact with the output pads 15. An insulating layer 26 isformed on the surface of the IC chip body 10 excluding the areas of thebumps. Next, a predetermined set of the bumps 21 is connected togetherby an output coupling lead wire 22, to which an external outputelectrode 24 is connected.

In accordance with the second embodiment, each of the multiple powerelements 11A and 11B is constituted of a multiplicity of divisionalelements 11A-1-11B-2. The divisional elements belonging to differentpower elements are sequentially arranged in juxtaposition to therebyreduce relative variations in the characteristics of the power elements.Moreover, crossing of the output wires 14A-1-42B-2 is eliminated tosuppress their layout area. In addition, only one rewiring layer 20 isused to provide the non-crossing output coupling wires 22A and 22B.Furthermore, since the rewiring layer 20 is formed to have the outputcoupling wires 22A and 22B that connect together the divisional elementsassociated with the same power element 11A or 11B, the semiconductordevice of the invention can be used as an ordinary IC chip.

FIG. 4 shows a structure of an IC chip body 10′ of the semiconductordevice according to a third embodiment of the invention.

In the IC chip body 10′ of FIG. 4, a power supply wire 16′ connectingthe divisional elements 11A-1-11B-2 to a power supply pad 17′ isarranged on the same plane without crossing any of the output wires14A-1-14B-2. Thus, the output wires 14A-1-14B-2 and the power supplywire 16′ can be formed using the same wiring layer. Other features ofthe arrangement of FIG. 4 are the same as for the IC chip body 10 ofFIG. 2A.

Formed on the IC chip body 10′ is the same rewiring layer 20 as shown inFIG. 2B.

In accordance with the third embodiment, although the length of thepower supply wire 16′ becomes larger as compared with that of the secondembodiment, the power supply wire 16′ can be formed together with theoutput wires 14A-1-14B-2 using the same wiring layer. The thirdembodiment can provide the same results as the second embodiment.

FIGS. 5A and 5B together show a structure of the semiconductor deviceaccording to a fourth embodiment of the invention. Particularly, FIG. 5Aillustrates the structure of an IC chip body 30, and FIG. 5B thestructure of a rewiring layer 40 formed on the IC chip body 30.

FIG. 5A shows an exemplary IC chip body 30 constituted of two powertransistors 31A and 31B (N=2) each divided into two divisional elements(M=2). The multiple divisional elements 31A-1, 31B-1, 31A-2, and 31B-2making up the power transistors 31A and 31B are arranged injuxtaposition in the order mentioned. The two divisional elements 31A-1and 31A-2 are controlled by a control signal supplied from a controlcircuit 32A via a signal wire 33A.

The output pad 35A-1 and 35A-2 associated with the divisional elements31A-1 and 31A-2 of the power transistor 31A are provided in proximity tothe upper ends of the respective divisional elements, as shown. Powersupply pads 37-1 and 37-3 are provided in proximity to the lower ends ofthe respective divisional elements, as shown. The output pads 35B-1 and35B-2 associated with the divisional elements 31B-1 and 31B-2 areprovided in proximity to the lower ends of the respective divisionalelements, as shown. The power supply pads 37-2 and 37-4 are provided inproximity to the upper ends of the respective divisional elements, asshown. Two sets of the divisional elements 31A-1 and 31A-2 and ofdivisional elements 31B-1 and 31B-2 are respectively supplied withcontrol signals from control circuits 32A and 32B via signal wires 33Aand 33B. Thus, the divisional elements 31A-1 and 31A-2 are driventogether as one power transistor 31A, and so are the divisional elements31B-1 and 31B-2 driven as one transistor 31B.

In this manner, the four (N×M) divisional elements 31A-1-31B-2 areprovided with respective power supply pads 37-1-37-4 and output pads35A-1-35B-2. These power supply pads 37-1-37-4 and output pads35A-1-35B-2 are connected to the divisional elements by the respectivepower supply wires and by the respective output wire (reference numberomitted in FIG. 5A).

The four (N×M) output pads 35A-1-35B-2 are arranged in such a way thattwo of them associated with the divisional elements 31A-1 and 31A-2belonging to the same power element 31A are each arranged at an angularposition (e.g. upper position) relative to the associated divisionalelement as shown, while two of them associated with the divisionalelements 31B-1 and 31B-2 belonging to the same power element 31B areeach arranged at another angular position (e.g. lower position) relativeto the associated divisional element as shown.

The four (N×M) power supply pads 37-1-37-4 are arranged in such a waythat two of them associated with the divisional elements 31A-1 and 31A-2belonging to the same power element 31A are each arranged at an angularposition (e.g. lower position) relative to the associated divisionalelement as shown, while two of them associated with the divisionalelements 31B-1 and 31B-2 belonging to the same power element 31B areeach arranged at another angular position (e.g. upper position) relativeto the associated divisional element.

Thus, the output wires and the power supply wires can be arranged inconsiderably short length without crossing one another by arranging theoutput pads 35A-1-35B-2 and the power supply pads 37-1-37-4 in theconfiguration as described above.

In the rewiring layer 40 of FIG. 5B formed on the IC chip body, theoutput bumps 41A-1, 41B-1, 41A-2, and 41B-2 and the power supply bumps43-1-43-4 are respectively provided on the IC chip body 30 in electricalcontact with the corresponding output pads 35A-1, 35B-1, 35A-2, and35B-2 and the corresponding power supply pads 37-1 to 37-4. Aninsulating layer is provided on the surface of the IC chip body 30excluding the areas of the bumps.

The output bumps 41A-1 and 41A-2 associated with the power transistor31A are connected together by an output coupling lead wire 42A, which isextended to a point where it is connected to an external outputelectrode 44A. The bumps 41B-1 and 41B-2 associated with the powertransistor 31B are connected together by an output coupling wire 42B,which is extended to a point where it is connected to an external outputelectrode 44B. The power supply bumps 43-1-43-4 are connected togetherby a power coupling wire 46, which is extended to a point where it isconnected to an external device.

Power supply electrodes 45-1 and 45-2 are connected to the powercoupling wire 46 at two points, which are, in the example shown herein,the power supply bumps 43-1 and 43-4. In this rewiring layer 40, thereis no crossing between the output coupling wires 42A and 42B nor betweenthe output coupling wires and the power coupling wire 46. Therefore, theoutput coupling wires 42A and 42B and the power coupling wire 46 can beimplemented by one electric conduction layer. Other features of thissemiconductor device are the same as those of the second and the thirdembodiments described above.

It is noted that in the fourth embodiment output wires and power supplywires never cross one another, that their lengths can be very short, andthat the same results can be attained as in the second embodiment.

FIGS. 6A and 6B together show a structure of the semiconductor deviceaccording to a fifth embodiment of the invention. Particularly, FIG. 6Ashows an exemplary structure of an IC chip body 50, and FIG. 6B shows anexemplary structure of a rewiring layer 60 formed on the IC chip body50.

The IC chip body 50 shown in FIG. 6A consists of two power transistors51A and 51B each divided into three divisional elements (N=2, M=3). Therewiring layer 60 of FIG. 6B formed on the IC chip body 50 is structuredto correspond to the three divisional elements of the respective powertransistors. The IC chip body 50 of FIG. 6A and the rewinding layer 60of FIG. 6B have the same structures as those of the fourth embodimentshown in FIGS. 5A and 5B except for the power transistors each dividedinto three divisions. Elements are denoted by numerals of 50's in FIG.6A and 60's in FIG. 6B.

More particularly, symbols 51A-1-51B-3 indicate the respectivedivisional elements of the power transistors 51A and 51B; symbols 52Aand 52B, control circuits; symbols 53A and 53B, signal wires; symbols55A-1-55B-3, output pads; and symbols 57-1-57-6, power supply pads.Further symbols 61A-1-61B-3 indicate output bumps; symbols 62A and 62B,output coupling wires; symbols 63-1-63-6, power supply bumps; symbols64A and 64B, external output electrodes; symbols 65-1 and 65-2, externalpower supply electrodes; and symbol 66, power supply coupling wires.

In the fifth embodiment, multiplicity M of divisional elements per powerelement can be increased while attaining the same results as the fourthembodiment.

FIGS. 7A and 7B show the structure of a semiconductor device accordingto a sixth embodiment of the invention. Particularly, FIG. 7A shows thestructure of an IC chip body 70, and FIG. 7B shows the structure of arewiring layer 80 formed on the IC chip body 70.

In the example shown in FIG. 7A, the IC chip body 70 has three powertransistors 71A, 71B, and 71C each consisting of two divisional elements(N=3, M=2). The rewiring layer 80 formed on the IC chip body of FIG. 7Bis structured to correspond to the two divisional elements of therespective power transistors of the IC chip body 70. The IC chip body 70and the rewinding layer 80 have the same structures as those of thesecond embodiment shown in FIGS. 2A and 2B except for the three powertransistors each being divided into two divisional elements denoted bynumerals of 70's in FIG. 7A and 80's in FIG. 7B.

More particularly, symbols 71A-1-71C-2 denote the respective divisionalelements of the power transistors 71A, 71B, and 71C; symbols 72A, 72B,and 72C, control circuits; symbols 73A, 73B, and 73C, signal wires;symbols 74A-1-74C-2, output wires; symbols 75A-1-75C-2, output pads;symbols 76, power supply wires; and symbol 77, power supply pad. Furthersymbols 81A-1-81C-2 denote output bumps; symbols 82A, 82B, and 82C,output coupling wires; symbols 83, a power supply bump; symbols 84A,84B, and 84C, external output electrodes; and symbols 85, an externalpower supply electrode.

In this sixth embodiment, output wires can connect the respective blockson the same plane without crossing one another if the number N of powerelements is increased, thereby providing the same results as thepreceding embodiments.

Although the invention has been described above only for the cases withM≦3 or N≦3 , it will be apparent that the invention can be extended tocases with M>3 and N>3 , facilitating minimization of wiring resistanceand a wiring space in a semiconductor device.

What we claim is:
 1. A rectangular semiconductor device, comprising: afirst semiconductor element; a second semiconductor element; a firstconductor electrically connected to the first semiconductor element, thefirst conductor extending, in a plan view of the semiconductor device asseen from an obverse face thereof on which the first and secondsemiconductor elements are mounted, from the first semiconductor elementtoward one side of the semiconductor device; a second conductorelectrically connected to the second semiconductor element, the secondconductor extending, in the plan view of the semiconductor device, fromthe second semiconductor element toward the one side of thesemiconductor device; a third conductor electrically connecting thefirst and second conductors together parallel to at least the one sideof the semiconductor device; and a fourth conductor disposed over, andapart from, the third conductor so as to cross the third conductor inthe plan view of the semiconductor device, the fourth conductor being,at one end thereof, electrically connected to an internal circuit of thesemiconductor device, wherein, in the plan view of the semiconductordevice as seen with the one side thereof on a near side, a firstdistance from a first intersection, located on left of the fourthconductor, between the first and third conductors to the fourthconductor is shorter than a second distance from a second intersection,located on right of the fourth conductor, between the second and thirdconductors to the fourth conductor.
 2. The semiconductor deviceaccording to claim 1, wherein the first semiconductor element iscontrolled by a control circuit connected thereto.
 3. The semiconductordevice according to claim 1, wherein the second semiconductor element iscontrolled by a control circuit connected thereto.
 4. The semiconductordevice according to claim 2, wherein the second semiconductor element iscontrolled by the control circuit connected thereto.
 5. Thesemiconductor device according to claim 1, wherein the fourth conductoris, at another end thereof, connected to an electrode.